1. Field of the Invention
The present invention relates to imaging devices and, in particular, to a CMOS active pixel image sensor cell design that substantially reduces photosensor leakage. An n-isolation layer formed under the pixels reduces cross-talk to simplify integration with digital logic and to reduce blooming.
2. Discussion of the Related Art
In order to meet the increasing need for high speed, "smart" image sensor devices, it is becoming necessary to integrate the image sensor array with other digital circuitry that controls the operation of the array and processes the array output. Integration of the image sensors with complimentary-metal-oxide-semiconductor (CMOS) support circuitry would be most desirable because of the low power consumption characteristics, maturity and common availability of CMOS technology.
Charge coupled devices (CCDs) are currently the most widely used technology for image sensors. However, CCDs are very power intensive and, due to their inherent sequential read out, have inefficient charge transfer characteristics unsuited for many high fidelity imaging applications. Furthermore, CCDs are not easily integrated with CMOS circuits due to complex fabrication requirements and high cost.
U.S. Pat. No. 5,289,023, issued to Carver A. Mead on Feb. 22, 1994, discloses an active pixel image sensor technology based upon a single npn poly-emitter bipolar phototransistor that is used both as an integrating photosensor and a select device. The Mead imager exhibits high sensitivity at low light levels, operates over a wider dynamic range than can be achieved with CCDs, and, because of its single-transistor photosensor, requires a relatively small cell array area. While the Mead technology offers great promise for the future, it has some drawbacks such as difficulty in obtaining good beta matching in the poly-emitter bipolar devices, the typical problems associated with fabricating buried layers and the high leakage sensitivity of the array.
S. K. Mendes. et al., "Progress In CMOS Active Pixel Image Sensors," SPIE, Vol. 2172, pp. 19-29, describe an active pixel sensor technology that is inherently CMOS compatible. Referring to the FIG. 1A schematic and the FIG. 1B timing diagram of the Mendes et al. publication, the imaging structure consists of a photogate PG with a floating diffusion output node FD separated by a transfer gate TX. The pixel unit cell also contains a reset transistor R, the input transistor of a first source-follower and a row selection transistor X. The read out circuit, which is common to an entire column of pixels, includes a load transistor VLN of the first source-follower and two sample and hold circuits for storing the signal level and the reset level. Each sample and hold circuit consists of a sample and hold switch (SHS or SHR) and capacitor (CS or CR) and a second source-follower and column selection transistor (Y1 or Y2). The load transistors of the second set of source-followers (VLP1 and VLP2) are common to the entire array of pixels.
In the operation of the FIG. 1A circuit, the rail voltages are set at 5 V and 0 V and the transfer gate TX is biased at 2.5 V. During signal integration, photogenerated electrons are collected under the photogate PG which is biased at 5 volts. The reset transistor R is biased at 2.5 V to act as a lateral anti-blooming drain, allowing excess charge to flow to the reset drain. The row-selection transistor X is biased off at 0 V. Following signal integration, the pixels of an entire row are read out simultaneously. First, the pixels in the row to be read out are addressed by enabling row selection switch X. Then, the floating diffusion output node FD of the pixel is reset by briefly pulsing the reset gate R to 5 V. This resets the floating diffusion output node FD to approximately 3.5 V. The output of the first source-follower is sampled onto capacitor CR at the bottom of the column by enabling sample and hold switch SHR. Then. photogate PG is pulsed low to 0 V, transferring the signal charge to the floating diffusion output node FD. The new output voltage is sampled onto capacitor CS by enabling sample and hold switch SHS. The stored reset and signal levels are sequentially scanned out through the second set of source-followers by enabling column address switches Y1 and Y2. The timing sequence for this operation is shown in FIG. 1B.
One of the biggest issues to be addressed when integrating an imaging array into a CMOS process is junction leakage on the photocollector. FIG. 2 shows photocollector junction leakage data for a conventional CMOS process. Note that the periphery component of the junction leakage is 100.times. the area component for V.sub.R =5 V at room temperature (T=25.degree. C.). This is because the active area edge is a region of high interface state density and, furthermore, is a region of high stress which acts as a gettering site for defects. Typically this peripheral leakage limits the dynamic range of the output of a CMOS active pixel sensor to about 8 bits. While suitable for some applications, 8-bit dynamic range does not affect the image quality required in other cases. For example, production of an image having 35 mm photographic quality requires about 10-bit dynamic range.
Furthermore, the motivation for building an imaging array utilizing a CMOS process is to allow integration with an analog to digital converter (ADC), thereby facilitating a digital-out imaging product. However, cross-talk between the digital CMOS circuitry of the ADC and the image array is a concern.